1. Field of the Invention
The present invention relates generally to semiconductor devices having a trench structure with a conductive layer buried in a trench provided in a main surface of a semiconductor substrate with an insulating layer therebetween and manufacturing methods thereof, and more specifically, to a semiconductor device having a trench structure with the above insulating layer and conductive layer formed to extend from the inside of a trench provided in a main surface of a semiconductor substrate to a prescribed region on the main surface of the semiconductor substrate and a manufacturing method thereof.
2. Description of the Background Art
In recent years, there have been demands for reduction of chip sizes and improvement of performances in semiconductor devices having a trench structure. Trench widths must be reduced accordingly. If a trench width is reduced too much, however, it would be difficult to directly form a contact in the conductive layer buried in the trench. It is therefore a generally practiced approach to lead out the conductive layer to be buried in the trench from the inside of the trench to the surface of the semiconductor substrate for contact with an input/output terminal electrode on the surface of the semiconductor substrate.
An insulated gate bipolar transistor having a trench structure (hereinafter simply referred to as "IGBT") will be described as an example of a semiconductor device having such a trench structure in which a conductive layer is led out from the inside of a trench to a semiconductor substrate surface. FIG. 44 is a plan view showing an IGBT having a conventional trench structure.
Referring to FIG. 44, a plurality of trenches 113 are provided in a prescribed region in a main surface of a substrate (not shown). n type emitter diffusion layers 106 are provided between prescribed regions of trenches 113. An emitter electrode 111 is formed on n type diffusion layers 106. Emitter electrode 111 and n type emitter diffusion layers 106 are electrically connected through contact portions 115.
An n type polycrystalline silicon layer 108 is formed buried in a trench 113 and extending from the inside of trench 113 to the main surface of the substrate. A gate electrode 111a is formed partially overlapping n type polycrystalline silicon layer 108. Gate electrode 111a and n type polycrystalline silicon layer 108 are electrically connected through a contact portion 114.
Now, a cross section of the IGBT having such a plan view structure will be described. FIG. 45 is a cross sectional view taken along line Y2--Y2 in FIG. 44. FIG. 46 is a cross sectional view taken along line Y1--Y1 in FIG. 44. FIG. 47 is a cross sectional view taken along line Y3--Y3.
With reference to these three cross sectional views, the structure of the IGBT will be described in more detail. Referring to FIG. 45, formed on a main surface of a p+ type monocrystalline silicon substrate 101 are an n+ type silicon epitaxial layer 102, an n- type silicon epitaxial layer 103, and a p type diffusion layer 104. These stacked layers form a substrate. A collector electrode 112 is formed on the back surface of p+ type monocrystalline silicon substrate 101.
On the main surface of the substrate, trench 113 having a bottom in n- type silicon epitaxial layer 103 and p type diffusion layer 104. A silicon oxide film 107 is formed on the inner surface of trench 113 and on the surface of p type diffusion layer 104. n type polycrystalline silicon layer 108 is formed on the surface of silicon oxide film 107, extending from the inside of trench 113 onto the surface of p type diffusion layer 104.
An interlayer insulating layer 109 is formed covering the surfaces of n type polycrystalline silicon layer 108 and p type diffusion layer 104. A barrier metal layer 110 is formed on a prescribed region of the surface of interlayer insulating layer 109. Emitter electrode 111 is formed on barrier metal layer 110. In interlayer insulating layer 109, an opening portion is provided in a prescribed region on the extension of n type polycrystalline silicon layer 108 on the surface of p type diffusion layer 104. Barrier metal layer 110 and electrode 111a described above are formed in the opening portion. Thus, contact portion 114 for gate electrode 111a and n type polycrystalline silicon layer 108 is formed.
Now, referring to FIG. 46, the structure of another cross section of the above IGBT will be described. Referring to FIG. 46, a p type base diffusion layer 105 is formed in a prescribed region of n- type silicon epitaxial layer 103. n type emitter diffusion layer 106 is formed on p type base diffusion layer 105. n type emitter diffusion layer 106 and emitter electrode 111 are electrically connected through contact portion 115.
On the sidewall of trench 113, as illustrated in FIG. 46, n type emitter diffusion layer 106, p type base diffusion layer 105, and then n- type silicon epitaxial layer 103 are sequentially formed. Thus formed MOS transistor has on the sidewall of trench 113 n type polycrystalline silicon layer 108 as a gate electrode, n type emitter diffusion layer 106 as a source region, and n- type silicon epitaxial layer 103 as a drain region.
Now, referring to FIG. 47, the structure of yet another cross section of the above IGBT will be described. Referring to FIG. 47, p type diffusion layer 104 described above is formed linked to p type base diffusion layer 105. n type emitter diffusion layer 106 is formed on p type base diffusion layer 105. n type emitter diffusion layer 106 is electrically connected to emitter electrode 111 through contact portion 115.
The operation of the conventional IGBT will be briefly described in conjunction with FIG. 46. Referring to FIG. 46, as described above, n channel MOS transistor is formed on the sidewall of trench 113 in the IGBT.
The n channel MOS transistor has n type polycrystalline silicon layer 108 functioning as a gate, silicon oxide film 107 functioning as a gate insulating layer, and n type emitter region 106 and n- type silicon epitaxial layer 103 functioning as source/drain regions. The operation of the IGBT will be controlled by the n channel MOS transistor.
The operation of the above IGBT until it is turned on will be described. In order to turn on IGBT, a prescribed positive potential is applied to a collector electrode 112, emitter electrode 111 is connected to ground, and a prescribed positive potential is applied to n type polycrystalline silicon layer 108.
The n channel MOS transistor is thus turned on. Electrons are then injected into n- type silicon epitaxial layer 103. At the time, since the positive potential is applied to collector electrode 112, holes are introduced into n- type silicon epitaxial layer 103 from the inside of p+ type silicon polycrystalline substrate 101.
Then, the above electrons and holes are recombined in n- type silicon epitaxial layer 103. Current is thus made to flow from collector electrode 112 to emitter electrode 111. In other words, the IGBT is turned on.
The off state of the IGBT will be described. In order to turn off the IGBT, n type polycrystalline silicon layer 108 is kept from application of a potential for example. In such a case, the n channel MOS transistor is turned off. Thus, electrons are not supplied into n- type silicon epitaxial layer 103 unlike the above case. Thus, electrons and holes will not be recombined unlike the above case. As a result, current does not flow from collector electrode 112 to emitter electrode 111. In other words, the IGBT is turned off.
Referring to FIGS. 49 to 60, a method of manufacturing a conventional IGBT having the above-described structure will be described. FIGS. 49 to 54 are cross sectional views showing first to sixth steps in a process of manufacturing the conventional IGBT, with the cross sections corresponding to FIG. 45.
FIGS. 55 to 60 are cross sectional views showing the first to sixth steps in the process of manufacturing the conventional IGBT, with the cross sections corresponding to the cross section shown in FIG. 46.
Referring to FIGS. 49 to 55, n+ type monocrystalline silicon epitaxial layer 102 and n- type monocrystalline silicon epitaxial layer 103 are sequentially formed on a main surface of p+ type monocrystalline silicon substrate 101 through epitaxial growth. Note that for simplicity of description, the stacked layer structure of p+ type monocrystalline silicon substrate 101, n+ type monocrystalline silicon epitaxial layer 102, and n- type monocrystalline silicon epitaxial layer 103 will be hereinafter simply referred to as "substrate".
A silicon oxide film 118 is formed on the surface of n- type monocrystalline silicon epitaxial layer 103. p type diffusion layer 104 and p type base diffusion layer 105 are formed on the surface of n- type monocrystalline silicon epitaxial layer 103 by means of photolithography, p type impurity ion implantation, and impurity diffusion techniques.
Referring to FIGS. 50 and 56, by means of photolithography, n type impurity ion implantation, and impurity diffusion techniques, n type emitter diffusion layer 106 is formed on the surface of p type base diffusion layer 105. Then, a silicon oxide film 119 is formed on the entire surface if the main surface of the substrate by CVD (Chemical Vapor Deposition) or the like.
Referring to FIGS. 51 and 57, silicon oxide film 119 is patterned into a prescribed form by photolithography and etching. Using silicon oxide film 119 as mask, the main surface of the substrate is anisotropically etched. A trench 113 is formed in the main surface of the substrate as a result.
Referring to FIGS. 52 and 58, oxidation treatment is conducted in order to remove damages made at the time of silicon etching for forming trench 113 described above. An oxide film formed by the oxidation treatment (not shown) and silicon oxide film 119 described above are then removed away. Then, a silicon oxide film 107 to be a gate oxide film is formed by means of thermal oxidation.
At the time, as described in IEEE TRANSACTIONS 0N ELECTRON DEVICES, VOL, ED-34, NO. 8, AUGUST, 1987, P.1681-P.1687, the upper end corner portion 117 of the sidewall of trench 113 has such a shape that the tip end forms an acute angle. The upper end corner portion 117 of the sidewall of trench 113 having such a shape is generally called "horn". FIG. 48 shows the horn (the upper end corner portion 117 of the sidewall of trench 113) being enlarged.
After silicon oxide film 107 is thus formed, polycrystalline silicon layer 108 containing an n type impurity is formed on the entire main surface of the substrate by CVD or the like.
Referring to FIGS. 53 and 59, resist 120 patterned into a prescribed shape is formed on n type polycrystalline silicon layer 108 by photolithography. Using patterned resist 120 as mask, n type polycrystalline silicon layer 108 is patterned.
At the time, n type polycrystalline silicon layer 108 is subjected to etching treatment for a relatively long period of time so that n type polycrystalline silicon layer 108 will not be left other than at a desired region on the main surface of the substrate. The upper surface of n type polycrystalline silicon layer 108 filling trench 113 is overetched and thus positioned below the main surface of the substrate.
Referring to FIGS. 54 and 60, after removal of patterned resist 120, interlayer insulating layer 109 is formed on the entire main surface of substrate by means of CVD.
Then, interlayer insulating layer 109 is patterned into a prescribed form by photolithography and etching, barrier metal layer 110 and emitter electrode 111 and gate electrode 111a formed of A or the like are formed in a prescribed region on interlayer insulating layer 109. Collector electrode 112 is formed on the back surface of p+ type monocrystalline silicon substrate 101. Through the above steps, the conventional IGBT shown in FIGS. 44 to 47 is formed.
The IGBT having the conventional trench structure described above is however encountered with the following problems. As illustrated in FIG. 48, the oxidation treatment for removal of damages formed at the time of silicon etching after formation of trench 113 and the oxidation treatment for forming silicon oxide film 107 produce horn 117 at the upper end corner portion of the sidewall of trench 113.
The shape of horn 117 is such a shape that the tip end portion substantially makes an acute angle. The thickness t of silicon oxide film 107 on horn 117 will be smaller than the thickness t1 of silicon oxide film 107 positioned on the sidewall of trench or on the surface of p type diffusion layer 104.
n type polycrystalline silicon layer 108 is formed to cover such horn 117 and silicon oxide film 107. n type polycrystalline silicon layer 108 which functions as a gate is supplied with a prescribed potential.
At the time, with horn 117 of such a shape, an electric field between n type polycrystalline silicon layer 108 to be a gate and the substrate is concentrated in the vicinity of horn 117. In addition, the thickness t of silicon oxide film 107 positioned on horn 117 is thin. As a result, the breakdown voltage of silicon oxide film 107 is greatly reduced in the vicinity of the region to form horn 117.
The following two approaches have been suggested for preventing the breakdown voltage of silicon oxide film 107 from being reduced.
The first approach is disclosed in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 8, AUGUST, 1987, P.1681-P.1687. The first approach is based on oxidation conditions of silicon. More specifically, according to the above document, it is described that horn 117 as described above is not formed at an oxidation temperature as high as about 1100.degree. C., and the upper end corner portion on the sidewall of trench 113 is rounded.
Thus rounding the upper end corner portion on the sidewall of trench 113 relaxes the concentration of electric field at the portion, and the breakdown voltage of silicon oxide film 107 positioned on the upper end corner portion of the sidewall of trench 113 can be improved.
According to the first approach, however, oxidation is conducted at a temperature as high as about 1100.degree. C. as described above, and therefore the structure of an impurity diffusion layer which has been previously formed can change.
Meanwhile, the second approach for improving the breakdown voltage of silicon oxide film 107 at the upper corner portion of the sidewall of trench 113 is disclosed in Japanese Patent Laying-Open Nos. 64-57623, 63-166230 or the like. These documents disclose a method of rounding such an upper end corner portion on the sidewall of trench 113 by means of chemical dry etching. However, thus simply rounding the upper end corner portion on the sidewall trench 113 has a limit in the effect of relaxing electrical field intensity without increasing the size of devices. The reason will be described in conjunction with FIG. 61.
FIG. 61 is a graph showing calculation results of the intensities of electric fields at the flat portion and the corner portion. In FIG. 61, the abscissa represents radius of curvature (r)/oxide film thickness (T.sub.ox) at the corner portion, while the ordinate represents electric field intensity (Er) at the corner portion/electric field intensity (Ep) at the flat portion.
Referring to FIG. 61, for an oxide film thickness of 0.1 .mu.m and a radius of curvature at the corner portion of 0.3 .mu.m, the electric field intensity at the corner portion is 1.25 times as large as that at the flat portion. As illustrated in FIG 61, in order to further relax the electric field intensity, the radius of curvature r of the corner portion must be increased. Thus increasing the radius of curvature (r) of the corner portion can impair reduction of the size of devices.
In view of the above, simply rounding upper end corner portion on the sidewall of trench 113 has its limit in improving the breakdown voltage of an insulating layer (silicon oxide film) positioned on the upper end corner portion of the sidewall of the trench without increasing the size of the device.
Note that it might be possible to secure the breakdown voltage at the upper end corner portion of the sidewall of trench 113 by increasing the thickness of silicon oxide film 107 besides the above first and second approaches. Silicon oxide film 107 however functions as a gate insulating layer for the MOS transistor for driving the IGBT, and therefore cannot be increased in thickness more than a necessary level. Therefore, it would also be difficult to improve the breakdown voltage of silicon oxide film 107 positioned on the upper end corner portion of the sidewall of trench 113 by this method.